1. Field of the Invention
The invention relates generally to sputtering of materials. In particular, the invention relates to the magnets enhancing plasma sputtering.
2. Background Art
Sputtering, alternatively called physical vapor deposition (PVD), is widely used to deposit layers of metals and related materials in the fabrication of semiconductor integrated circuits. Conventional sputter reactors include a planar target of the metal to be sputtered in opposition to the wafer being coated. A working gas, typically argon, fills the chamber at low pressure. In DC sputtering, a negative voltage is applied to the target sufficient to discharge the argon into a plasma. The positive argon ions are attracted to the negatively biased target with sufficient energy that they sputter metal atoms from the target. Some of the sputtered metal atoms strike the wafer and coat it with a layer of the metal. In reactive sputtering, most often of metal nitrides, nitrogen, oxygen, or other reactive gas is additionally filled into the chamber. The reactive gas reacts with the sputtered metal atoms at the surface of the wafer forming a metal nitride layer on the wafer surface.
The multiple wiring levels representative of advanced integrated circuits include inter-level dielectric layers, typically of silicon dioxide or related silicate glass, separating neighboring pairs of generally horizontally extending electrical interconnects. Vias are electrical plugs extending vertically through the inter-level dielectric layers to interconnect the different wiring levels. A via is formed by etching a narrow hole through the exposed dielectric layer and then filling the holes with the metallization after a proper barrier or seed layer has been coated onto the sidewalls and bottom of the via hole. The increased capacity of advanced integrated circuits is achieved in large part by shrinking the horizontal dimensions of its elements. The minimum width of vias is being pushed to 0.18 μm and below. A minimum width of 0.07 μm is being planned for the not too distant future. However, for a number of reasons, the thickness of the inter-level dielectric layers needs to be at least about 0.7 μm thick and may be even more for some complex structures. The result is that the aspect ratio of via holes is being pushed to above 5 for current products, and an aspect ratio of 10 or even higher is contemplated.
Sputtering has long been used to sputter aluminum for horizontal interconnections and to simultaneously fill via holes extending between metallization levels. Special sputtering techniques have been developed to deposit thin layers into narrow and deep vias to act as barrier and seed layers. Typical barrier materials include titanium, tantalum, tungsten, and their nitrides, all of which can be sputtered. Silicidation metals can also be sputtered. These layers need be only a few nanometers thick, but they must coat the sides of the via holes, a difficult but achievable process in sputtering. Copper is replacing aluminum in advanced integrated circuits for the metallization materials. Although most of the copper is deposited by electrochemical plating (ECP), a thin copper seed layer is required to initiate the ECP growth and to provide a plating electrode. Again, the copper seed layer must coat the side of the via holes.
Sputtering into high aspect-ratio holes is a difficult task since the sputtering produces an approximately isotropic sputtering pattern. One general technique causes a large fraction of the sputtered metal atoms to be ionized. A negative electrical bias is applied to the pedestal electrode supporting the wafer being sputter coated to accelerate the metal ions to a high perpendicular velocity so that they penetrate deeply within high aspect-ratio holes.
Several types of plasma sputter reactors have been developed which enable a high metal ionization fraction. One such reactor is the SIP+™ reactor available from Applied Materials, Inc. of Santa Clara, Calif. Gopalraja et al. describes an initial design in U.S. Pat. No. 6,277,249. A more complete design is described by Gopalraja et al. in U.S. patent application Ser. No. 09/703,601, filed Nov. 1, 2000, and by Subramani et al. in U.S. Pat. No. 6,406,599. The latter two references are incorporated here by reference in their entireties. The SIP+ reactor, which will be described in detail later, includes a complexly shaped target having an annular vault facing the wafer. The vault includes inner and outer sidewalls and a roof bridging the sidewalls.
The technology incorporated into the SIP+ reactor derives many of its advantages from the strength and shape of magnets placed behind the vault sidewalls and roof. However, the high magnetic intensities introduce their own complexities and artifacts, which need to be controlled and in some cases compensated. Producing uniform sputter deposition is a challenge when the annular vaulted target and its magnetrons are distinctly non-uniform in the radial direction. Although remarkable process results have been achieved, further improvements are desired.